1. Field of the Invention
The present invention relates to a liquid crystal display device and its manufacture method, and more particularly to a liquid crystal display device of an active matrix type with auxiliary capacitors which seemingly increases each pixel capacitance and to its manufacture method.
2. Description of the Related Art
A conventional thin film transistor (TFT) type liquid crystal display device will be described with reference to FIGS. 6A and 6B.
FIG. 6A is a plan view showing the layout of a TFT substrate. Formed on the surface of a transparent substrate are a plurality of control bus lines 100 extending in a horizontal direction in FIG. 6A and a plurality of data bus lines 101 extending in a vertical direction. Each bus line 100 is electrically insulated by an insulating film from each data bus line 101 at their cross points. Between adjacent two control bus lines 100, a capacitor bus line 102 is disposed extending in generally parallel with the control bus lines 100. Similarly, each capacitor bus line 102 is electrically insulated from each data bus line 101 at their cross points. The capacitor bus line 102 is applied with a constant potential, for example, a ground potential.
A TFT 103 is formed near at each cross point between the control bus 100 and data bus line 101. The drain electrode of TFT 103 is connected to the corresponding data bus line 101, and the corresponding bus line 100 serves also as the gate electrode of TFT 103. The source electrode of TFT 103 is connected to the corresponding pixel electrode 104. This pixel electrode 104 is disposed in an area surrounded by the corresponding control and data bus lines 100 and 101.
An auxiliary capacitor pattern 105 branched from the capacitor bus line 102 is disposed in parallel with and adjacent to the data bus line 101 in each area where the pixel electrode 104 is disposed. The auxiliary capacitor pattern 105 is overlapped with the corresponding pixel electrode 104. An auxiliary capacitor C.sub.S is formed between the pixel electrode 104 and the capacitor bus line 102 and auxiliary capacitor pattern 105.
A common electrode substrate is disposed facing the TFT substrate, and liquid crystal material is accommodated in a space between these two substrates.
FIG. 6B is an equivalent circuit diagram of one pixel of the liquid crystal display device shown in FIG. 6A. A liquid crystal capacitor C.sub.LC is formed between the pixel electrode 104 and common electrode, and the auxiliary capacitor C.sub.S is connected in parallel with the liquid crystal capacitor. A stray capacitor C.sub.DS is formed between the pixel electrode 104 and data bus line 101.
If a potential at the data bus line 101 varies while TFT 103 is non-conductive, i.e., while this pixel is not selected, the potential at the pixel electrode 104 also varies because of capacitive coupling by the stray capacitor C.sub.DS. This potential change .DELTA.V is given by: EQU .DELTA.V=CV.sub.DS /(CV.sub.DS +C.sub.LC +C.sub.S) (1)
This voltage fluctuation causes crosstalk (luminance variation) which depends on a slope of luminance along the display screen scan direction (parallel with the data bus line 101) and on a display pattern.
This voltage fluctuation .DELTA.V is suppressed by the auxiliary capacitor C.sub.S in parallel with the liquid crystal capacitor C.sub.LC of the device shown in FIG. 6A. If a large auxiliary capacitor C.sub.S is formed by using the capacitor bus line 102 and auxiliary capacitor pattern 105, the effects of voltage fluctuation on the data bus line 101 can be eliminated and the display quality can be improved.
As shown in FIG. 6A, the auxiliary capacitor pattern 105 is disposed adjacent to the data bus line 101 so as to provide as large an aperture ratio as possible. Because of this proximate layout, insufficient strength of an insulating film between the auxiliary capacitor pattern 105 and dada bus line 101 may occur or electrical short circuit therebetween may occur due to position alignment errors of these patterns.
A short circuit recovery method will be described with reference to FIG. 7 which is a schematic plan view of a TFT substrate.
In a display area 110, TFT's 103 and pixel electrodes 104 are disposed in a matrix pattern. A plurality of repair wiring patterns 111 are formed at upper, lower and right peripheral regions of this display area 110. For example, ten repair wiring patterns 111 are prepared. Each repair wiring pattern 111 intersects with data bus lines 101 at the upper and lower peripheral regions of the display area 110.
If there is a short circuit between the auxiliary capacitor pattern 105 and data bus line 101, the data bus line 101 is cut at points D.sub.1 and D.sub.2 on both sides of the short circuit point. Cutting the data bus line is performed, for example, through radiation of laser beam.
The data bus lines 101 cut at the points D.sub.1 and D.sub.2 are connected to one of the repair wiring patterns 111 at their cross points. This connection is performed, for example, by radiation of laser beam to the connection points. The data bus lines 101 cut in the display area 110 are therefore electrically connected again by the repair wiring pattern 111. These repair works require a number of processes, and their success possibility is small. Furthermore, since the repair wiring patterns 111 are required to be formed in the peripheral region (called a frame region) of the display area 110, it is difficult to reduce the area of the frame region. If an electrical short circuit is formed in a plurality of pixels connected to one data bus line, repairs are impossible. Similarly, if an electrical short circuit is formed on data bus lines more than the number of repair wiring patterns 111, repairs are impossible.